Multiprocessor Hardware/Software Codesign (CODES)

• Recently completed dissertation (December 1999) in the area of specification and design methodology of high-performance middleware-based multiprocessor digital signal processing systems using performance modeling:
  
  
A Model-Continuous Specification and Design Methodology
For Embedded Multiprocessor Signal Processing Systems


• Active participant in the specification forums for the industry standard signal processing computational middleware standard, VSIPL (Vector Scalar Image Processing Library), as well as MPI/RT (real-time MPI). Currently co-chairing the VSIPL Forum.
• Advanced heterogeneous multicomputer software tool-based application research and development.
• Ported and benchmarked multiprocessor applications for radar, sonar, intelligent character and forms recognition, theatre-level weather modeling, radio astronomy, and MIMO digital controllers.

• Designed, developed and implemented real-time multi-tasked signal processing algorithms and firmware for a satellite modem using C, assembler, and SPOX.
• Performed algorithm analysis and design via a variety of computer model simulations and analytical analyses on military satellite communication waveforms (bandwidth/power efficient and coded modulations).
• Performed signal processing algorithm analysis and design of real-time airborne monopulse radar signal processors using fixed point hardware.

• Developed and implemented algorithms optimized for speed and efficiency to search for targets in digitized images of a simulated radar screen.
• Researched, examined, and compared various techniques for implementing a hybrid spectral-spatial classification algorithm to operate on Landsat data.

• Real-time embedded microprocessor-based hardware, ROM-based hardware, and firmware design and implementation.
• System software analysis, design, and development (JOVIAL, FORTRAN, assembler).
• Advanced systems analysis (air-to-ground and tank-antitank simulations).

• Reviewed and/or contributed to over a dozen books on DSP and digital controls using Matlab and Simulink.
• Taught  upper-level undergraduate courses on digital system architecture and design, circuits, electronics, signals and systems, and communications.
• Hardware: 
• Real-time embedded multicomputers: Mercury Computer Systems (heterogeneous i860, PPC, SHARC) and SKY Computers (i860). 
• Workstations: Sun , PC's, Macs, SGI. 
• DSP's: Texas Instruments TMS320xx DSP's, Analog Devices 21xx fixed point DSP's. 
• Mainframes: VAX and DEC minicomputers. 
• Software: 
• Operating Systems: UNIX, MC/OS, VxWorks, VMS, SPOX. 
• Programming Languages: Perl, Talaris and Application Configuration Language (ACL), C, FORTRAN, Matlab, various assembly languages (Intel 808x, Analog Devices ADSP 21x DSPs, Texas Instruments TMS320x DSPs, DEC PDP11 family), Matrixx, PL/1, JOVIAL, AHPL, Basic. 
• Development Tools:  Parallel Application System (PAS), SuperVision multiprocessor debugger, GNU debugger (gdb), GNU profiler (gprof), BB&N Gist multiprocessor event analyzer, Texas Instruments TMS320C40 Simulator, Analog Devices ADSP 2100 Simulator. 
• Applications:  Alta SPW, Simulink, Stateflow, eArchitect. 

Previous Positions:

SKY Computers 
Application Engineer, 1993-1995. 

The MITRE Corporation 
Member of the Technical Staff, 1990-1993. 

Raytheon Missile Systems Laboratory 
Design Engineer, 1987-1990. 

Georgia Institute of Technology 
Graduate Research Institute, 1987. 

FSU/FAMU College of Engineering 
Visiting Assistant Professor, 1985-1987. 

The University of Central Florida 
Graduate Teaching Assistant, 1983-1985. 

NCR Industrial Computer Systems 
Digital Design Engineer, 1981-1983. 

Martin Marietta Aerospace 
Co-op Student and Software Technician, 1976-1981.

1. R. S. Janka and L. M. Wills, “Virtual Benchmarking of Embedded Multiprocessor Signal Processing Systems,” submitted to IEEE Design and Test of Computers, 2000, pp. 26.
2. R. S. Janka, “A Model-Continuous Specification and Design Methodology for Embedded Multiprocessor Signal Processing Systems,” a Ph.D. dissertation in the School of Electrical and Computer Engineering. Atlanta, Georgia: Georgia Institute of Technology, December 1999, pp. xxiii, 225.
3. R. S. Janka and L. M. Wills, “A Novel and Improved Specification and Design Methodology for Large COTS-based Multiprocessing Radar Signal Processors,” accepted for 32nd IEEE Southeastern Symposium on System Theory (SSST Y2K), FAMU-FSU College of Engineering, Tallahassee, Florida, 2000.
4. R. Janka, R. Judd, J. Kepner, J. Lebak, M. Richards, and D. Schwartz, “The Vector, Signal, and Image Processing Library (VSIPL) Standard for High Perforomance Computing: Interface and Product Status of  v1.0,” presented at SC99: High Performance Networking and Computing Conference, Portland, OR, 1999.
5. R. S. Janka, R. Judd, J. Lebak, M. A. Richards, and D. A. Schwartz, “API and Product Status of the v1.0 Vector, Signal, and Image Processing Library (VSIPL),” presented at Third Annual Workshop on High Performance Embedded Computing, Lexington, MA, 1999.
6. R. Janka and L. Wills, “Considering Models of Computation in Developing a New Specification and Design Methodology for Large Real-Time Embedded Multiprocessor Signal Processing Systems,” presented at accepted for the IEEE International Workshop on Intelligent Signal Processing (WISP'99), Budapest, Hungary, 1999.
7. R. Janka, “VSIPL: Computational Middleware for Portable Real-Time Embedded Multicomputing Application Software,” presented at The International Conference on Signal Processing Applications and Technology and DSP World Workshops (DSP World - ICSPAT), Orlando, FL, 1999.
8. R. Janka and L. Wills, “Early System-Level Design Exploration of Large DSP Systems Targeted for Real-Time Embedded COTS Multiprocessors,” presented at The International Conference on Signal Processing Applications and Technology and DSP World Workshops (DSP World - ICSPAT), Orlando, FL, 1999.
9. R. Janka, “Models of Computation for Specification and Design Methodology Frameworks for Parallel and Distributed Real-Time Embedded Multiprocessor Signal Processing Systems,” presented at The 1999 International Conference on Parallel and Distributed Processing Techniques and Applications (PDPTA '99), Las Vegas, NV, 1999.
10. R. Janka, “A New Development Framework Based on Efficient Middleware for Real-Time Embedded Heterogeneous Multicomputers,” presented at 1999 IEEE Conference and Workshop on Engineering of Computer-Based Systems (ECBS '99), Nashville, Tennessee, 1999.
11. J. Scheer, M. Richards, R. Janka, et al., "Mobile Artillery Tracking Radar System Concept Design," GTRI Final Technical Report submitted to the Army Research Laboratory, July 1998.
12. R. Janka, “Multiprocessor Software Development for RACEway-based Real-Time Signal Processing Systems,” presented at Real-Time Computer Show & Conference, San Jose, CA, 1997.
13. R. Janka, “The Use of Application Software Mapping Tools for Real-Time Embedded Multiprocessor Signal Processing Systems,” presented at DSP World Spring Design Conference, Washington D.C., 1997.
14. R. Janka, “Bridging the Development Gap of Real-Time Embedded Multiprocessor Signal Processing Systems,” presented at DSP World Spring Design Conference, Washington D.C., 1997.
15. R. Janka, “Graphical Tools Enhance Productivity,” Electronic Engineering Times, July 7, 1997, pp. 66.
16. R. Janka, A. Clouard, O. Debon, and J.-C. Mison, “Graphical Application Software Development for Deployable Heterogeneous Multicomputers,” presented at Eighth International Conference on Signal Processing Applications and Technology, San Diego, CA, 1997.
17. Cournoyer, A., R. Janka, and W. Ralston, "Design Specification of the DUSTE-5 UHF Modem", MITRE Technical Report, 1994.
18. Janka, R., "Trellis-Coded Modulation:  Fundamentals and Recent Developments", MITRE "M-Document" M92-(TBD), in process upon departure.
19. Janka, R., "Trellis-Coded Modulation:  New Descriptions and Evaluations", MITRE "M-Document" M92-(TBD), in process upon departure.
20. Janka, R., AAAM Digital Subsystem Test Requirements Specification (1990), ACSP IIR Digital Roughing Filter Analysis (1989), Standard Missile-2 Block IV (Aegis Extended Range):  Software Detailed Level Design Document (Guided Test Vehicle Signal Processor Program) (1988), Raytheon internal reports and specifications.
21. Janka, R., "Integration of Multispectral and Spatial Classification Techniques of Landsat Data", Georgia Tech Research Institute internal report, 1987.
22. Simons, F., R. Harden, and R. Janka, "Systems Analysis Polynomial Algorithms Optimized for Speed and Minimum Memory, " Proceedings of the ASEE Annual Conference, June 1985.
23. Janka, R.(1983), The Use of Computer Vision to Close the Control Loop of a Robot Arm, M. Sc., The University of Central Florida.
24. Janka, R., Design and Implementation Specification:  Programmable Interface Translation System, (1983), Design and Implementation Specification:  Magnetics Adapter Board Firmware, (1982), Design and Implementation Specification:  Programmable Serial Interface Board, (1981), NCR internal reports.